1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof and more particularly to a double-gate MOS transistor having two gate electrodes.
2. Description of the Related Art
Conventionally, a double-gate MOS transistor having two gate electrodes is known. The double-gate MOS transistor has a feature that the short channel effect can be suppressed in comparison with a MOS transistor having a single gate electrode. Therefore, it is expected to realize an extremely fine MOS transistor having a channel length shorter than 25 nm by using the double-gate structure.
A fabricating method of the double-gate MOS transistor is explained with reference to FIG. 1A to FIG. 1F. FIG. 1A to FIG. 1F are cross-sectional views sequentially showing the fabricating steps of a double-gate MOS transistor.
First, as shown in FIG. 1A, an element isolation region 110 is formed on a silicon substrate 100 by use of a LOCOS (LOCal Oxidation of Silicon) method, for example. Then, a back-gate insulating film 120 and back-gate electrode 130 are sequentially formed on the surface of the silicon substrate 100. Next, as shown in FIG. 1B, an insulating film 140 is formed on the surface of the silicon substrate 100 by the CVD (Chemical Vapor Deposition) method. After this, as shown in FIG. 1C, the insulating film 140 is polished and made flat by the CMP (Chemical Mechanical Polishing) method. Then, a silicon substrate 150 is adhered or bonded onto the insulating film 140 to obtain the structure shown in FIG. 1D. Further, as shown in FIG. 1E, the silicon substrate 100 is polished and made thin by the CMP method or the like so as to form a silicon active layer 160. After this, a front-gate insulating film 170 and front-gate electrode 180 are formed on the silicon active layer 160. Next, side wall insulating films 190, 190 are formed on the side surfaces of the front-gate electrode 180 and source and drain regions 200, 200 are formed in the silicon active layer 160 to complete a double-gate MOS transistor as shown in FIG. 1F.
According to the double-gate MOS transistor having the structure shown in FIG. 1F, the gate delay time can be significantly reduced. As a result, high-speed operation and low power consumption in an LSI can be attained.
However, with the conventional fabricating method of the double-gate MOS transistor, the film thickness of the silicon active layer 160 is determined by the polishing step of the silicon substrate 100 using the CMP method. In this case, if the polishing process is performed by use of the CMP method, high controllability of the film thickness of the silicon active layer 160 cannot be attained. Further, the film may, in some cases, be non-uniform in thickness over its entire surface. As a result, it becomes difficult in some cases to fabricate a MOS transistor having characteristics as designed.